Short Title:Digital System Verification
Full Title:Digital System Verification
Module Code:DIGV H6001
 
Credits: 7.5
Field of Study:Electronics and automation
Module Delivered in 1 programme(s)
Reviewed By:JAMES WRIGHT
Module Author:RICHARD GAHAN
Module Description:To enable the student to design an appropriate digital system verification strategy for a block, a multi-block or digital system. To implement portions of a verification strategy using systemVerilog or other appropriate language
Learning Outcomes
On successful completion of this module the learner will be able to:
LO1 To evaluate a system and propose and defend a verification strategy and write a verification plan which implements a best practice verification strategy.
LO2 To design verification tests, write a test plan and write code to implement the tests in an appropriate verification language e.g. systemVerlog
LO3 To execute a coverage driven verification methodology and to choose appropriate toolsets dependant on design complexity.
LO4 To implement effective design reviews and determine if design reviews have achieved their stated goal.
LO5 To apply BIST and SCAN techniques to ASIC designs.
LO6 To write a test report which demonstrates test coverage criteria
 

Module Content & Assessment

Course Work
Assessment Type Assessment Description Outcome addressed % of total Assessment Date
Assignment Evaluate state of the art verification techniques to design, define and document an overall test plan for a selected complex system. Defend test plan. 1 20.00 Week 4
Assignment Digital System testbench (constrainted random) coded in systemVerilog and demonstrated which complies to the digital portion of the test plan. Evaluate test results and report findings in a formal test report. Defence of report. 2,3,4,6 40.00 Week 10
Assignment Technical paper - Produce a technical paper on emerging techniques and approaches of particular relevance to digital systems verification. Make a presentation on the paper to peers and answer questions 1,3 15.00 Week 13
Assignment Time Constrained Assignments 4,5 25.00 Week 10
No End of Module Formal Examination

TU Dublin – Tallaght Campus reserves the right to alter the nature and timings of assessment

 

Module Workload

Workload: Full Time
Workload Type Workload Description Hours Frequency Average Weekly Learner Workload
Lecture Interactive Lecture 2.00 Every Week 2.00
Lab Lab/discussion 1.00 Every Week 1.00
Independent Learning Working on Assignments 9.00 Every Week 9.00
Total Weekly Learner Workload 12.00
Total Weekly Contact Hours 3.00
Workload: Part Time
Workload Type Workload Description Hours Frequency Average Weekly Learner Workload
Lecture Interactive Lecture 2.00 Every Week 2.00
Lab Lab/discussion 1.00 Every Week 1.00
Independent Learning Working on Assignments 9.00 Every Week 9.00
Total Weekly Learner Workload 12.00
Total Weekly Contact Hours 3.00
 

Module Resources

Recommended Book Resources
  • by Janick Bergeron... [et al.] 2006, Verification methodology manual for SystemVerilog, Springer New York [ISBN: 978-0-387-25538-5]
  • by Stuart Sutherland, Simon Davidmann, Peter Flake; foreword by Phil Moorby 2006, SystemVerilog for design, Springer New York [ISBN: 978-0-387-33399-1]
This module does not have any article/paper resources
This module does not have any other resources
 

Module Delivered in

Programme Code Programme Semester Delivery
TA_EEESD_M Masters of Engineering in Electronic Engineering in Electronic System Design 2 Mandatory