Short Title:Dig System Mod, Syn & Imp
Full Title:Dig System Mod, Syn & Imp
Module Code:DIGS H6002
 
Credits: 7.5
Field of Study:Electronics and automation
Module Delivered in 1 programme(s)
Reviewed By:JAMES WRIGHT
Module Author:RICHARD GAHAN
Module Description:To enable the student write synthesizable code of a digital system, in Verilog and VHDL. To enable the student to synthesize their design from FPGA and ASIC libraries.
Learning Outcomes
On successful completion of this module the learner will be able to:
LO1 To select an appropriate design process flow and to select tools to implement the process flow for small and very large projects.
LO2 To write synthesizable Verilog and VHDL for a designed digital system to optimise for performance or area
LO3 To synthesize a digital system using a modern synthesis tool (e.g. synopsys or Synplify) to meet IO and block performance metrics and to verify the integrity of a structural netlist using simulation techniques.
LO4 To optimize the coding of a digital system to take account of restrictions in the architecture of a target library e.g. memory instantiation.
LO5 To parameterize the coding of a digital system to take account of flexible design choices.
LO6 To analyse the timing aspects of a synthesized and routed design and solve timing/area related problems using innovative synthesis/layout strategies
LO7 To estimate power usage of a design and ways to minimize power usage.
 

Module Content & Assessment

Course Work
Assessment Type Assessment Description Outcome addressed % of total Assessment Date
Assignment Evaluate target synthesis libraries by performing tests to benchmark expected performance. Use results to code target design to optimise for area/ speed performance. Write code in Verilog and VHDL. Write report justifying key coding decisions. 2,3 20.00 Week 4
Assignment Unit Test plan written, Testbench coded and tests passing on RTL and structural netlist. 1,2 20.00 Week 6
Assignment Generate Synthesis scripts to maximise system performance and compare performance results to required. Use HDL modifications and/or script modifications to improve performance. Generate Timing analysis report and analysis/commentry of report 4,5,6,7 20.00 Week 10
Assignment Generate Layout and floorplan scripts to target section of FPGA and IO pins. Modify code, synthesis and layout scripts to maximize performance. Write Post Layout timing analysis Report and comment on results. Justify results. 1,2,3,4,5,6,7 20.00 Week 13
Assignment Time constrained assessments 1,2,3,4,5,6,7 20.00 Ongoing
No End of Module Formal Examination

TU Dublin – Tallaght Campus reserves the right to alter the nature and timings of assessment

 

Module Workload

Workload: Full Time
Workload Type Workload Description Hours Frequency Average Weekly Learner Workload
Lecture Interactive lecture 2.00 Every Week 2.00
Lab Practical 1.00 Every Week 1.00
Independent Learning Time Assignment Work 10.00 Every Week 10.00
Total Weekly Learner Workload 13.00
Total Weekly Contact Hours 3.00
Workload: Part Time
Workload Type Workload Description Hours Frequency Average Weekly Learner Workload
Lecture Interactive lecture 2.00 Every Week 2.00
Lab practical 1.00 Every Week 1.00
Independent Learning Assignment Work 10.00 Every Week 10.00
Total Weekly Learner Workload 13.00
Total Weekly Contact Hours 3.00
 

Module Resources

Recommended Book Resources
  • Michael D. Ciletti, 2005, Advanced Digital Design With the Verilog Hdl [ISBN: 978-0131678446]
  • Zainalabedin Navabi 2006, Verilog digital system design, McGraw-Hill New York [ISBN: 978-0071445641]
  • Nazeih M Botros, 2005, HDL Programming Fundamentals : VHDL and Verilog [ISBN: 978-1584508557]
This module does not have any article/paper resources
This module does not have any other resources
 

Module Delivered in

Programme Code Programme Semester Delivery
TA_EEESD_M Masters of Engineering in Electronic Engineering in Electronic System Design 1 Mandatory