Short Title:Digital FSM Design
Full Title:Digital FSM Design
Module Code:DIGS H4001
 
Credits: 5
Field of Study:Electronics and automation
Module Delivered in 2 programme(s)
Reviewed By:JOHN ANDREW DONNELLAN
Module Author:RICHARD GAHAN
Module Description:To enable the student to analyse and design digital circuits using state machine and other techniques. To implement digital designs using Flip flops and combinational logic. To assess and evaluate real world effects like setup and hold time issues, signal reflections and relevant real world issues.
Learning Outcomes
On successful completion of this module the learner will be able to:
LO1 Design synchronous state machines and circuits to solve medium level real world engineering problems.
LO2 Design address decoding and transaction interface solutions for microprocessor accesses to external devices
LO3 Identify and analyse potential problems and design relevant solutions for problems associated with the electrical characteristics of logic gates e.g. static timing analysis, hazards, setup/hold timing violations, undershoot / overshoot (termination schemes)
LO4 Design digital circuits to accomodate asynchronous inputs and to analyse the failure rate of these interfaces
LO5 Design digital systems that involve pipeline functionality when required
LO6 Analyse digital circuits and describe their behaviour in FSMs (Finite State Machines)
LO7 Write a technical report adhering to prescribed guidelines
LO8 Participate in a constructive way in teams on Engineering tasks.
 

Module Content & Assessment

Course Work
Assessment Type Assessment Description Outcome addressed % of total Assessment Date
Continuous Assessment Design and analyse solutions to a range of digital design problems, individually or in teams. professionally document and defend solutions. 1,2,3,4,5,6,7,8 30.00 n/a
End of Module Formal Examination
Assessment Type Assessment Description Outcome addressed % of total Assessment Date
Formal Exam End-of-Semester Final Examination 1,2,3,4,5,6 70.00 End-of-Semester

TU Dublin – Tallaght Campus reserves the right to alter the nature and timings of assessment

 

Module Workload

Workload: Full Time
Workload Type Workload Description Hours Frequency Average Weekly Learner Workload
Lecture No Description 2.00 Every Week 2.00
Lab No Description 2.00 Every Week 2.00
Independent Learning No Description 3.00 Every Week 3.00
Total Weekly Learner Workload 7.00
Total Weekly Contact Hours 4.00
Workload: Part Time
Workload Type Workload Description Hours Frequency Average Weekly Learner Workload
Lecture No Description 2.00 Every Week 2.00
Lab No Description 2.00 Every Week 2.00
Independent Learning No Description 3.00 Every Week 3.00
Total Weekly Learner Workload 7.00
Total Weekly Contact Hours 4.00
 

Module Resources

Recommended Book Resources
  • Michael D. Ciletti 2011, Advanced digital design with the Verilog HDL, Prentice Hall Boston [ISBN: 978-0136019282]
  • Randy H. Katz 2005, Contemporary logic design, Pearson Prentice Hall Upper Saddle River, N.J. [ISBN: 978-0201308570]
  • John F. Wakerly 2006, Digital design, Pearson/Prentice Hall Upper Saddle River,New Jersey [ISBN: 0-131863894]
  • Howard W. Johnson, Martin Graham 1993, High-speed digital design, Prentice Hall Englewood Cliffs, N.J. [ISBN: 978-0133957242]
This module does not have any article/paper resources
This module does not have any other resources
 

Module Delivered in

Programme Code Programme Semester Delivery
TA_EAELE_B Bachelor Degree in Engineering (Honours) in Electronic Engineering 7 Mandatory
TA_EELEC_B Bachelor of Engineering (Honours) in Electronic Engineering -- Add On Year 1 Mandatory