Short Title:Digital System Design 1
Full Title:Digital System Design 1
Language of Instruction:English
Module Code:DIGS H6001
 
Credits: 7.5
Field of Study:Electronics and automation
Module Delivered in 1 programme(s)
Reviewed By:JAMES WRIGHT
Module Author:RICHARD GAHAN
Module Description:To enable the student to analyse new problems and formulate structured design solutions using digital circuits which require a multi input multi output system controller. To assess and take account of real world architecture restrictions of some available technologies in the design solution.
Learning Outcomes
On successful completion of this module the learner will be able to:
LO1 To analyse digital circuits and describe their behaviour in FSMs (Finite State Machines)
LO2 To design synchronous state machines to solve real world engineering problems.
LO3 To evaluate a complex problem and architect a solution to partition a digital design problem into logical subsections and to design solutions to these subsections that integrates well with the overall solution.
LO4 Code a small digital system comprising an FSM and logic in verilog
LO5 To design systems that meet quality, reliability and cost metrics.
LO6 To be able to document a technical solution adhering to prescribed guidelines.
LO7 To be able to participate in a constructive way in teams on Engineering tasks.
 

Module Content & Assessment

Course Work
Assessment Type Assessment Description Outcome addressed % of total Assessment Date
Assignment To take an unfamiliar problem and solve it using digital design techniques. Estimate performance of solution from target library datasheets. 1,2,3,6 5.00 Week 3
Assignment To analyse an unfamiliar semi-complex system and partition in into digital subsystems and complete design including coding in verilog. 1,2,3,5,6,7 15.00 Week 7
Assignment Mini-Project (in Teams where applicable). To design a solution to a complex Digital System Design problem targeted to selected FPGA device. Output is a paper design and documentation. 1,2,3,5,6,7 20.00 Week 12
Presentation Mini-Project presentation - defense to peers and assessment of teamwork criteria (where applicable). 1,2,3,5,6,7 10.00 Week 13
End of Module Formal Examination
Assessment Type Assessment Description Outcome addressed % of total Assessment Date
Formal Exam End-of-Semester Final Examination 1,2,3 50.00 End-of-Semester

TU Dublin – Tallaght Campus reserves the right to alter the nature and timings of assessment

 

Module Workload

Workload: Full Time
Workload Type Workload Description Hours Frequency Average Weekly Learner Workload
Lecture Lecture 2.00 Every Week 2.00
Lecturer Supervised Learning Practical 1.00 Every Week 1.00
Independent Learning Assignment Work 10.00 Every Week 10.00
Total Weekly Learner Workload 13.00
Total Weekly Contact Hours 3.00
Workload: Part Time
Workload Type Workload Description Hours Frequency Average Weekly Learner Workload
Lecture Lecture 2.00 Every Week 2.00
Lecturer Supervised Learning Practical 1.00 Every Week 1.00
Independent Learning Assignment Work 10.00 Every Week 10.00
Total Weekly Learner Workload 13.00
Total Weekly Contact Hours 3.00
 

Module Resources

This module does not have any book resources
This module does not have any article/paper resources
This module does not have any other resources
 

Module Delivered in

Programme Code Programme Semester Delivery
TA_EEESD_M Masters of Engineering in Electronic Engineering in Electronic System Design 1 Mandatory