Short Title:Digital Systems Design II
Full Title:Digital Systems Design II
Language of Instruction:English
Module Code:DIGS H6003
 
Credits: 7.5
Field of Study:Electronics and automation
Module Delivered in 1 programme(s)
Reviewed By:JAMES WRIGHT
Module Author:RICHARD GAHAN
Module Description:To enable the student to gain and practice the skills necessary to architect and design solutions to leading edge digital design problems. To enable the student to review and evaluate advanced digital systems and published literature.
Learning Outcomes
On successful completion of this module the learner will be able to:
LO1 To apply pipeline techniques to solve constrained design problems.
LO2 To evaluate between alternate memory technologies and design high performance digital systems using appropriate memory technology
LO3 To Analyse loosely defined block interfacing proposals, identify problems, generate and evaluate potential solutions
LO4 To architect, design, document and justify complex digital systems requiring pipelining, parallelization and data flow analysis techniques from an ill defined description of system requirements
LO5 To design solutions involving multi asynchronous clock system. To evaluate and identify scenarios to which an asynchronous circuit design solution is appropriate, to design and document an asynchronous circuit solution and to verify its operation against specifications.
 

Module Content & Assessment

Course Work
Assessment Type Assessment Description Outcome addressed % of total Assessment Date
Assignment To Design a Solution to a complex interface problem. The design documentation Package to consist of those elements set out in the assignment. 1,2,3,4 20.00 Week 6
Assignment Examine a complex ill-defined problem and solve it using a multi-clock asynchronous interfacing system design approach. Complete and document the design. 5 20.00 Week 11
Assignment Implement the Design(above) and Functionally Verify it. Document the verification approach, results and the evaluation of the results. Present and Defend results. 4,5 20.00 Week 13
Assignment Time Constrained Assignments under supervision if/when required. 1,2,3,4,5 20.00 Ongoing
Assignment Research paper - Produce a technical paper on an emerging technology of particular relevance to digital systems design. Make a presentation on the paper to their peers and answer questions e.g. latest RAM technology, latest interface buses, latest synthesis techniques, new design methods. 4 20.00 Week 13
No End of Module Formal Examination

TU Dublin – Tallaght Campus reserves the right to alter the nature and timings of assessment

 

Module Workload

Workload: Full Time
Workload Type Workload Description Hours Frequency Average Weekly Learner Workload
Lecture Interactive lecture 2.00 Every Week 2.00
Lab Practical 1.00 Every Week 1.00
Independent Learning Working on Assignments 9.00 Every Week 9.00
Total Weekly Learner Workload 12.00
Total Weekly Contact Hours 3.00
Workload: Part Time
Workload Type Workload Description Hours Frequency Average Weekly Learner Workload
Lecture Interactive Lecture 2.00 Every Week 2.00
Lab Lab/discussion 1.00 Every Week 1.00
Independent Learning Working on Assignments 9.00 Every Week 9.00
Total Weekly Learner Workload 12.00
Total Weekly Contact Hours 3.00
 

Module Resources

Recommended Book Resources
  • by Richard F. Tinder 2000, Engineering digital design, Academic Press San Diego [ISBN: 0-12-691295-5]
This module does not have any article/paper resources
Other Resources
  • Free Online Book in PDF format: Jens Spars 2006, Asynchronous Circuit Design, Technical University of Denmark.
 

Module Delivered in

Programme Code Programme Semester Delivery
TA_EEESD_M Masters of Engineering in Electronic Engineering in Electronic System Design 2 Mandatory