Short Title:Digital Microprocessor Design
Full Title:Digital Microprocessor Design
Language of Instruction:English
Module Code:DIGS H4002
 
Credits: 5
Field of Study:Electronics and automation
Module Delivered in 3 programme(s)
Reviewed By:JAMES WRIGHT
Module Author:RICHARD GAHAN
Module Description:To bring the student through the various aspects of complex digital system design and analysis using examples. To enable students to design and analyse a digital system solving a real world technical problem. To enable the student to design a simple uP.
Learning Outcomes
On successful completion of this module the learner will be able to:
LO1 Design a multi-block digital system to solve real world problem, code in verilog and implement on FPGA.
LO2 Design a simple 4 or 8 bit microprocessor from flip-flops and memory.
LO3 Design an ARM/AMBA(or chosen) based system.
LO4 Design and analyse a real time system based on the ARM(or chosen) microprocessor
LO5 Discuss and describe various cache architecture advantages and disadvantages and design a cache memory for a microprocessor from basic memory components.
LO6 Write a technical report adhering to prescribed guidelines.
LO7 Participate in a constructive way in teams on Engineering tasks.
 

Module Content & Assessment

Course Work
Assessment Type Assessment Description Outcome addressed % of total Assessment Date
Continuous Assessment Labs/Tutorials: Explore techniques for designing high performance digital circuits along with methods for evaluating their properties. Term Assignments 1,2,3,4,5,6,7 30.00 Ongoing
End of Module Formal Examination
Assessment Type Assessment Description Outcome addressed % of total Assessment Date
Formal Exam End-of-Semester Final Examination 1,2,3,4,5 70.00 End-of-Semester

TU Dublin – Tallaght Campus reserves the right to alter the nature and timings of assessment

 

Module Workload

Workload: Full Time
Workload Type Workload Description Hours Frequency Average Weekly Learner Workload
Lecture No Description 2.00 Every Week 2.00
Lab No Description 2.00 Every Week 2.00
Independent Learning No Description 3.00 Every Week 3.00
Total Weekly Learner Workload 7.00
Total Weekly Contact Hours 4.00
Workload: Part Time
Workload Type Workload Description Hours Frequency Average Weekly Learner Workload
Lecture No Description 2.00 Every Week 2.00
Lab No Description 2.00 Every Week 2.00
Independent Learning No Description 3.00 Every Week 3.00
Total Weekly Learner Workload 7.00
Total Weekly Contact Hours 4.00
 

Module Resources

Recommended Book Resources
  • John P. Hayes 2002, Computer architecture and organization, WCB/McGraw-Hill Boston [ISBN: 9780071159975]
  • John L. Hennessy, David A. Patterson; with contributions by Andrea C. Arpaci-Dusseau... [et al.], Computer architecture [ISBN: 978-0123704900]
This module does not have any article/paper resources
This module does not have any other resources
 

Module Delivered in

Programme Code Programme Semester Delivery
TA_EAELE_B Bachelor Degree in Engineering (Honours) in Electronic Engineering 8 Elective
TA_EELEC_B Bachelor of Engineering (Honours) in Electronic Engineering -- Add On Year 2 Elective
TA_EAENS_B Bachelor of Engineering (Hons) in Engineering Software 8 Elective