Short Title:Digital Design with Verilog
Full Title:Digital Design with Verilog
Language of Instruction:English
Module Code:CAEE H3001
 
Credits: 5
Field of Study:Electronics and automation
Module Delivered in 3 programme(s)
Reviewed By:JAMES WRIGHT
Module Author:PATRICK O FRIEL
Module Description:This module is a practical introduction to the Verilog hardware description language. Students will learn to write Verilog code, using FPGA Development tools, to model digital devices and systems. Problem solving will be explored while simulating digital designs and implementing them on a Field Programmable Gate Array (FPGA) prototyping board.
Learning Outcomes
On successful completion of this module the learner will be able to:
LO1 Use development tools to model digital designs and implement them on an FPGA prototyping board.
LO2 Describe the internal architecture and the benefits of using an FPGA
LO3 Describe the design flow from specification to implementation
LO4 Write Verilog code to model digital designs using a structured design methodology
LO5 Write test benches to test and verify digital designs
LO6 Write scripts to run simulation and implementation tools
LO7 Write reports to document the design and verification process
LO8 Define a problem, analyse , design, implement and evaluate a solution as part of a project, while considering all ethical implications.
LO9 Communicate effectively as part of a team, as well as formally presenting their findings verbally and in written documents.
 

Module Content & Assessment

Course Work
Assessment Type Assessment Description Outcome addressed % of total Assessment Date
Continuous Assessment Design 1, Demo + Report 1,4,5,7 10.00 Week 4
Continuous Assessment Design 2, Demo + Report 1,4,5,7 10.00 Week 8
Continuous Assessment Design 3, Quiz, Demo + Report 1,4,5,6,7 10.00 Week 12
Continuous Assessment Project 8,9 10.00 Week 12
End of Module Formal Examination
Assessment Type Assessment Description Outcome addressed % of total Assessment Date
Formal Exam End-of-Semester Final Examination 2,3,4,5,6 60.00 End-of-Semester

TU Dublin – Tallaght Campus reserves the right to alter the nature and timings of assessment

 

Module Workload

Workload: Full Time
Workload Type Workload Description Hours Frequency Average Weekly Learner Workload
Lecturer/Lab Design Exercises 4.00 Every Week 4.00
Independent Learning Design Exercises 3.00 Every Week 3.00
Total Weekly Learner Workload 7.00
Total Weekly Contact Hours 4.00
Workload: Part Time
Workload Type Workload Description Hours Frequency Average Weekly Learner Workload
Lecturer/Lab Design Exercises 4.00 Every Week 4.00
Independent Learning Design Exercises 3.00 Every Week 3.00
Total Weekly Learner Workload 7.00
Total Weekly Contact Hours 4.00
 

Module Resources

Recommended Book Resources
  • Thomas L. Floyd, Digital fundamentals [ISBN: 0-138146462]
  • Haskell, R. E. & Hanna D. M 2008, Learning by example using Verilog: basic digital design with a BASYS FPGA board, 1st ed Ed., LBE Books
This module does not have any article/paper resources
This module does not have any other resources
 

Module Delivered in

Programme Code Programme Semester Delivery
TA_EAELE_B Bachelor Degree in Engineering (Honours) in Electronic Engineering 6 Mandatory
TA_EAELE_D Bachelor of Engineering in Electronic Engineering 6 Mandatory
TA_EELEC_D Bachelor of Engineering In Electronic Engineering - Add On Year 2 Mandatory